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A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology

A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology

TYPE OF PUBLICATION

Publication in Conference Proceedings / Workshop

AUTHORS

M. Mestice, J. Feldmann, J. Lappas, M. Esmaeilpour, C. Weis, N. Wehn

PUBLISHER

YEAR OF PUBLICATION

2025

ISSN

DOI

https://doi.org/10.1109/SOCC66126.2025.11235391

LINK TO THE REPOSITORY

https://kluedo.ub.rptu.de/frontdoor/index/index/docId/13119

LINK TO THE PUBLICATION

https://ieeexplore.ieee.org/document/11235391