From 8-12 June 2026, the EUPILOT project participated in RISC-V Summit Europe 2026 in Bologna, Italy, joining researchers, industry representatives, and the wider RISC-V community to discuss the latest developments in open hardware technologies.

Throughout the event, EUPILOT was represented at the RISC-V@BSC (Barcelona Supercomputing Center) booth alongside other RISC-V projects and research initiatives led by the Barcelona Supercomputing Center (BSC) such as DARE and Barcelona Zettascale Lab, highlighting European efforts to advance RISC-V technologies for high-performance computing.

The Summit began with Bond & Build: Our Journey in Tech, a networking initiative hosted by Teresa Cervero (BSC) to support and connect women participating in the event. The official opening followed on 9 June with welcome remarks from Nick Kossifidis (FORTH), Teresa Cervero (BSC), and Andrea Bartolini (University of Bologna).

EUPILOT researchers contributed to the technical programme through a poster presentation by Oumaima Matoussi (CEA), InterFinder: A Framework for Memory Interference Analysis in RISC-V Vectors.

The project was also featured during the workshop Advancing RISC-V Adoption in HPC and Cloud Environments, organised by the RISER project and Manolis Marazkis (ICS-FORTH), where Carlos Puchol (BSC) presented RISC-V Accelerators: Experiences from the European PILOT Project, sharing insights gained through EUPILOT’s work on accelerator technologies.

Access all the presentations here.

The Summit also featured a keynote by Luca Benini (ETH), RISC-V: Enabling Open Physical AI, highlighting the growing role of open instruction set architectures in supporting the next generation of AI and computing systems.

EUPILOT’s participation at RISC-V Summit Europe 2026 provided an opportunity to present project results, exchange knowledge with the European RISC-V community, and contribute to discussions shaping the future of open hardware for HPC and AI.

Visit our Events page to find out where you can meet us next.