Our project collaborator, John Davis from Barcelona Supercomputing Centre, is at the RISC-V Summit 2022 in the session titled “Is RISC-V HPC? RISC-V is HPC!“. The talk is on December 13, from 2:15 pm – 2:35 pm in Pacific Standard Time (PST) UTC -8 in San Jose, CA.
See the presentation:
Technology trends are mandating software/hardware co-design for HPC systems. An Open Standard Instruction Set Architecture (ISA) like RISC-V enables a powerful co-design paradigm. Currently, RISC-V lacks the maturity of other closed ISAs available on the market. Many in the HPC community are unfamiliar with the details of RISC-V and/or incorrectly associate the ISA and development efforts as being limited to the embedded community. However, today, a focused and dedicated effort is underway within the RISC-V community (well-funded companies, government support, and research) to bring RISC-V into the HPC space. As part of this presentation, we will update the larger community on our efforts (identify the HPC gaps, provide standardized ISA solutions and lead the effort to build up the ecosystem) and solicit feedback to prioritise the next steps. We will present the status of the current SW and HW RISC-V ecosystem focusing on HPC. This is a call to action to address the gaps and prioritize efforts that target HPC with RISC-V hardware and the associated software stack.