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Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

TYPE OF PUBLICATION

Publication in Conference Proceedings / Workshop

AUTHORS

Luca Colagrande, Luca Benini

PUBLISHER

YEAR OF PUBLICATION

2025

ISSN

DOI

https://doi.org/10.1109/DAC63849.2025.11132520

LINK TO THE REPOSITORY

https://arxiv.org/abs/2503.20590

LINK TO THE PUBLICATION

https://ieeexplore.ieee.org/document/11132520